• DocumentCode
    765176
  • Title

    Programmable active memories: reconfigurable systems come of age

  • Author

    Vuillemin, Jean E. ; Bertin, Patrice ; Roncin, Didier ; Shand, Mark ; Touati, Herve H. ; Boucard, Philippe

  • Author_Institution
    Paris Res. Lab., Digital Equipment Corp., Rueil-Malmaison, France
  • Volume
    4
  • Issue
    1
  • fYear
    1996
  • fDate
    3/1/1996 12:00:00 AM
  • Firstpage
    56
  • Lastpage
    69
  • Abstract
    Programmable active memories (PAM) are a novel form of universal reconfigurable hardware coprocessor. Based on field-programmable gate array (FPGA) technology, a PAM is a virtual machine, controlled by a standard microprocessor, which can be dynamically and indefinitely reconfigured into a large number of application-specific circuits. PAM´s offer a new mixture of hardware performance and software versatility. We review the important architectural features of PAM´s, through the example of DECPeRLe-1, an experimental device built in 1992. PAM programming is presented, in contrast to classical gate-array and full custom circuit design. Our emphasis is on large, code-generated synchronous systems descriptions; no compromise is made with regard to the performance of the target circuits. We exhibit a dozen applications where PAM technology proves superior, both in performance and cost, to every other existing technology, including supercomputers, massively parallel machines, and conventional custom hardware. The fields covered include computer arithmetic, cryptography, error correction, image analysis, stereo vision, video compression, sound synthesis, neural networks, high-energy physics, thermodynamics, biology and astronomy. At comparable cost, the computing power virtually available in a PAM exceeds that of conventional processors by a factor 10 to 1000, depending on the specific application, in 1992. A technology shrink increases the performance gap between conventional processors and PAM´s. By Noyce´s law, we predict by how much the performance gap will widen with time.
  • Keywords
    PLD programming; coprocessors; field programmable gate arrays; firmware; memory architecture; microprogramming; reconfigurable architectures; virtual machines; DECPeRLe-1; Noyce law; PAM programming; application-specific circuits; applications; architecture; code-generated synchronous system; field-programmable gate array; microprocessor; programmable active memories; reconfigurable hardware coprocessor; virtual machine; Application software; Circuit synthesis; Coprocessors; Costs; Field programmable gate arrays; Hardware; Microprocessors; Software performance; Space technology; Virtual machining;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/92.486081
  • Filename
    486081