Design of a high-performance IIR digital filter chip

The design of a novel high-performance IIR digital filter chip is presented. The chip has been implemented using 1.5 mu m double-layer metal CMOS technology. The filter chip operates on an 11-bit two´s-complement input data, a 12-bit two´s-complement coefficient word and produces a two´s-complement 14-bit output. The main component of the chip is a fine grained systolic array architecture that internally is based on a signed binary number representation (SBNR). In the paper, the design of the internal array is discussed along with the circuitry necessary to convert data from SBNR to a two´s-complement representation. Other important design issues, such as testing and clock distribution, are also addressed.