Performance of a RISC machine with two level caches

To improve computer system performance, small high-speed memories (caches) often accompany CPU complexes. With the advancement of VLSI densities, two levels of cache are becoming more common. The authors evaluate the performance of a computer with a two level cache using simulation techniques. The address stream that drives the simulator is gathered from an experimental RISC processor running a real-time, telephony application. A simple instruction set and high context switching within this code create address trace properties unique to RISC computers. To give insight into the characteristics of this trace, the locality properties of the address trace are investigated. The miss ratio and the average memory access time are used as the performance metrics. When the real-time telephony address trace is compared to address traces from other studies of time-sharing operating systems running on CISC processors, it was found to differ in the relative number of instruction address references.