Title :
An optimized compensation strategy for two-stage CMOS op amps
Author :
Palmisano, G. ; Palumbo, G.
Author_Institution :
Dipartimento Elettrico Elettronico e Sistemistico, Catania Univ., Italy
fDate :
3/1/1995 12:00:00 AM
Abstract :
An optimized compensation strategy for two-stage Miller-compensated CMOS operational amplifiers is presented. The output conductance of the buffer which avoids the right half-plane zero is profitably used to achieve a pole-zero compensation. Indeed, thanks to a proper choice of the buffer transconductance, the compensation for the pole due to the load capacitor is reached, thus providing better frequency performance
Keywords :
CMOS analogue integrated circuits; circuit stability; compensation; frequency response; operational amplifiers; poles and zeros; Miller-compensated circuits; buffer transconductance; frequency performance; load capacitor; optimized compensation strategy; output conductance; pole-zero compensation; two-stage CMOS op amps; Character generation; Circuit noise; FETs; High power amplifiers; Noise generators; Operational amplifiers; Thermal resistance; Topology; Transconductance; Voltage;
Journal_Title :
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on
