Inhibitory mechanism analysis of complexity O(N) MOS winner-take-all networks

Circuits that perform the winner-take-all (WTA) function are essential building blocks in analog parallel signal processors. We observe that VLSI implementations of the WTA function rely almost invariably on voltage-follower (VF) circuits for the transmission of the inhibitory signal over the network. Basic VF circuits present low resolution, however, and several modifications have been proposed in order to enhance the system performance. These modifications add local feedback to the system, being the global feedback still transmitted by a nested VF circuit. In this paper, we examine the role of MOS/VF circuits in hardware realizations of the WTA function and derive a general method for estimating the resolution gain attained when such modifications are introduced onto a basic VF system. We also examine implementations that do not make use of this kind of inhibitory channel, often presenting lower resolution and/or bigger circuit size