DocumentCode :
76569
Title :
A Novel Framework for the Design of Adaptable Reconfigurable Partitions for the Placement of Variable-sized IP Cores
Author :
Marques, Nicolas ; Rabah, Hassan ; Dabellani, Eric ; Weber, Simon
Author_Institution :
Inst. Jean Lamour (IJL), Univ. of Lorraine, Nancy, France
Volume :
6
Issue :
3
fYear :
2014
fDate :
Sept. 2014
Firstpage :
45
Lastpage :
48
Abstract :
This letter presents a novel framework for the design of adjustable reconfigurable partitions for the placement of variable-sized IP cores on embedded reconfigurable systems. It enables the rapid and easy to use methodology for the generation of adaptive computation and communication infrastructure for partial dynamic reconfiguration. The methodology allows an adaptable partition and efficient resource utilization for the placement of reconfigurable modules. The different steps of the proposed framework are detailed. Its effectiveness and benefits are demonstrated through the use of a practical example implemented on a tiled reconfigurable architecture.
Keywords :
embedded systems; field programmable gate arrays; industrial property; reconfigurable architectures; resource allocation; FPGA; adaptable partition; adaptable reconfigurable partitions design; adaptive computation; communication infrastructure; embedded reconfigurable systems; field programmable gate array; intellectual property cores; partial dynamic reconfiguration; reconfigurable modules placement; resource utilization; tiled reconfigurable architecture; variable-sized IP cores; Data mining; Field programmable gate arrays; Hardware; IP networks; Routing; Standards; Table lookup; Adaptable reconfiguration partition; design framework; dynamic partial reconfiguration; field-programmable gate arrays (FPGA); variable-sized IP cores;
fLanguage :
English
Journal_Title :
Embedded Systems Letters, IEEE
Publisher :
ieee
ISSN :
1943-0663
Type :
jour
DOI :
10.1109/LES.2014.2317254
Filename :
6797858
Link To Document :
بازگشت