DocumentCode :
765999
Title :
Performance Analysis of Digital Tanlock Loop
Author :
Lee, Jae Chon ; Un, Chong Kwan
Author_Institution :
Korea Advanced Institute of Science and Technology, Seoul, Korea
Volume :
30
Issue :
10
fYear :
1982
fDate :
10/1/1982 12:00:00 AM
Firstpage :
2398
Lastpage :
2411
Abstract :
In this paper, a nonuniform-sampling digital phaselocked loop (DPLL) called the digital tanlock loop (DTL), which uses a new type of phase error detector with linear phase characteristic, is studied. The main feature of the DTL is that the phase error detector, using the \\tan^{-1}(.) function with in-phase and quadrature samples of the incoming signal, has a linear characteristic with a period of 2π. Accordingly, the DTL can be characterized by a linear difference equation, thereby making it possible to analyze the loop easily, without approximation of nonlinearity as is usually done in analysis of a conventional DPLL with sinusoidal phase characteristic. The performances of the first- and second-order DTL\´s in the absence and presence of noise have been investigated by analysis and computer simulation. It is shown that the linear phase characteristic results in many attractive features in comparison to the conventional DPLL with the sinusoidal phase characteristic. These include insensitivity of the locking conditions to variation of input signal power, more noise immunity, wider lock range and less steady-state phase error of the first-order loop for an input with frequency offset, and much less sensitivity to initial phase errors in convergence of the second-order loop.
Keywords :
PLLs; Phase-locked loop (PLL); Computer errors; Computer simulation; Convergence; Detectors; Difference equations; Frequency; Performance analysis; Phase detection; Phase noise; Steady-state;
fLanguage :
English
Journal_Title :
Communications, IEEE Transactions on
Publisher :
ieee
ISSN :
0090-6778
Type :
jour
DOI :
10.1109/TCOM.1982.1095407
Filename :
1095407
Link To Document :
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