Efficient global strategy for designing and testing scanned sequential circuits

Scan design has been widely used for alleviating the burden of test generation. How to reduce the extra costs caused by the scan design becomes a major target. Previous approaches have tried individually to enhance the abilities of test generation algorithm and scan cell selection strategy. In contrast, a global strategy taking care of the close relationship between these factors and combining a new scan structure is proposed. Reducing the test application time which may dominate the cost testing a mass product is the goal of this research. First of all, a new scan structure named gradually-on (GO) structure which allows for the scan cells in the scan chain to be gradually turned on is used. Two assertions for the design of test generator are proposed next, and a fault list oriented test generation algorithm is developed in accordance with these two assertions. A simulation based partial scan methodology is finally introduced for selecting the suitable scanning flip-flops one by one through the means of sufficiently utilising the dynamic information generated during fault simulation. Experimental results show that overall consideration of scan design and test generation is able to speed up test generation and reduce a great amount of test application time