Manifestations of faults in single- and double-BJT BiCMOS logic gates

Combining the inherent advantages of bipolar and CMOS, BiCMOS is emerging as a major technology for high speed, high performance, digital and mixed signal applications. Logic behaviour of single- and double-BJT BiCMOS devices under transistor level shorts and opens is examined. In addition to sequential behaviour, some stuck open faults exhibit increased delay. While most stuck on faults can be detected by logic level testing, some of them can only be detected by monitoring the power supply current (I_DDQ monitoring). A stuck open fault in double-BJT BiCMOS device manifesting as enhanced dynamic I_DD current is shown. The faulty behaviour of bipolar (TTL) and CMOS logic families is compared with BiCMOS. Testability of both single- and double-BJT BiCMOS devices are discussed, along with a design for testability approach for detecting stuck open faults in S-BJT BiCMOS devices