Title :
A 40-ps high electron mobility transistor 4.1 K gate array
Author :
Kajii, Kiyoshi ; Watanabe, Yuu ; Suzuki, Masahisa ; Hanyu, Isamu ; Kosugi, Makoto ; Odani, Kouichiro ; Mimura, Takashi ; Abe, Masayuki
Author_Institution :
Fujitsu Ltd., Atsugi, Japan
fDate :
4/1/1988 12:00:00 AM
Abstract :
A high-electron mobility transistor (HEMT) 4.1 K-gate array has been developed, using a selective dry etching process and a MBE (molecular-beam epitaxy) growth technology. The circuit design uses direct-coupled FET logic (DCFL). The chip contains 4096 NOR gates, each with a 0.8-μm gate length, and measures 6.3 mm×4.8 mm. A basic gate delay of 40 ps has been achieved. A 16×16-bit parallel multiplier, used to test this array, has a multiplication time of 4.1 ns at 300 K, where the power dissipation is 6.2 W
Keywords :
VLSI; cellular arrays; digital arithmetic; field effect integrated circuits; integrated circuit technology; integrated logic circuits; molecular beam epitaxial growth; multiplying circuits; 0.8 micron; 16 bit; 300 K; 4.1 ns; 40 ps; 6.2 W; 6.3 mm; ASIC; DCFL; HEMT; MBE; NOR gates; VLSI; custom IC; direct-coupled FET logic; gate array; gate delay; gate length; high electron mobility transistor; molecular-beam epitaxy; multiplication time; parallel multiplier; power dissipation; selective dry etching process; Circuit synthesis; Dry etching; FETs; HEMTs; Length measurement; Logic circuits; Logic design; MODFETs; Molecular beam epitaxial growth; Semiconductor device measurement;
Journal_Title :
Solid-State Circuits, IEEE Journal of
