DocumentCode :
766497
Title :
A novel framework for logic verification in a synthesis environment
Author :
Kunz, Wolfgang ; Pradhan, Dhiraj K. ; Reddy, Subodh M.
Author_Institution :
Group for Fault-Tolerant Comput., Univ. of Potsdam, Germany
Volume :
15
Issue :
1
fYear :
1996
fDate :
1/1/1996 12:00:00 AM
Firstpage :
20
Lastpage :
32
Abstract :
A new methodology for formal logic verification of combinational circuits is presented. Specifically, a structural (logic network) approach is used, based on indirect implications derived by recursive learning. It is shown that implications can be used to capture similarity between designs. This is extended to formulate a hybrid approach, this structural (logic network) information is used to reduce the complexity of a subsequent functional method based on OBDDs. We demonstrate that OBDD-based verification can take great advantage of structural preprocessing in a synthesis environment where many small operations are performed that modify the circuit. The experimental results show that an effective combination can be achieved between memory efficient structural methods and powerful functional methods
Keywords :
Boolean functions; circuit CAD; circuit analysis computing; combinational circuits; formal verification; logic CAD; OBDD-based verification; binary decision diagrams; combinational circuits; formal verification; logic verification; ordered BDD; recursive learning; structural preprocessing; synthesis environment; Application software; Circuit synthesis; Combinational circuits; Error correction; Integrated circuit synthesis; Laboratories; Logic; Network synthesis; Process design; Very large scale integration;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.486269
Filename :
486269
Link To Document :
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