DocumentCode :
766546
Title :
On the integration of partitioning and global routing for rectilinear placement problems
Author :
Yeh, Chingwei ; Wang, Chi-Shong
Author_Institution :
Electr. Eng. Dept., Nat. Chung-Cheng Univ., Chiayi, Taiwan
Volume :
15
Issue :
1
fYear :
1996
fDate :
1/1/1996 12:00:00 AM
Firstpage :
83
Lastpage :
91
Abstract :
Rectilinear placement is an important process for mixed macro block/standard cells design due to frequent presence of preplaced macro blocks. A prevailing solution to this problem is to divide the rectilinear region into rectangular sub-regions and partition cells into these sub-regions before applying standard placement algorithms. For such a strategy to work, the partitioning objective must closely correlate with the global routing objective. In this paper, we propose a new method to integrate global routing with partitioning. The salient features of our approach consist of (1) a new edge cost model and its computation using an incremental assignment technique; (2) a resistive network analogy for net cost modeling and a randomized algorithm for resistance computation; (3) a robust partitioning framework that combines the ideas of (1) and (2). Also, a dynamic strategy is proposed to evaluate the performance of the algorithm. Our method has been tested on several benchmark circuits and displayed excellent results in terms of both wire length and routability
Keywords :
circuit layout CAD; computational complexity; graph theory; integrated circuit layout; iterative methods; logic CAD; logic partitioning; network routing; network topology; algorithm performance evaluation; dynamic strategy; edge cost model; global routing; incremental assignment technique; mixed macro block/standard cells design; network partitioning; placement algorithms; randomized algorithm; rectilinear placement problems; resistance computation; resistive network analogy; robust partitioning framework; Benchmark testing; Circuit testing; Computational modeling; Computer networks; Costs; Partitioning algorithms; Process planning; Robustness; Routing; Wire;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.486274
Filename :
486274
Link To Document :
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