Ratioed voter circuit for testing and fault-tolerance in VLSI processing arrays

Author

Belabbes, Nacer-Eddine ; Guterman, Alexandre J. ; Savaria, Yvon ; Dagenais, Michel

Author_Institution

Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada

Volume

43

Issue

2

fYear

1996

fDate

2/1/1996 12:00:00 AM

Firstpage

143

Lastpage

152

Abstract

Fault detection and fault-tolerance in modular processing arrays are reviving the use of majority voting techniques. In this paper, a simple voting circuit structure, called a ratioed voter, is analyzed to prove its reliable operation when Dynamic N-Modular Redundant (DNMR) tuples are configured for testing in fault-tolerant processing arrays. Its application in VLSI design for self-testing would lead to low area overhead and high diagnosability, both contributing to improve yield. Moreover, the flexibility of such a structure, which allows modulation of the voting level (N), permits a common approach for fabrication-time and on-line testing

Keywords

VLSI; fault diagnosis; integrated circuit design; integrated circuit yield; logic testing; majority logic; redundancy; sensitivity analysis; wafer-scale integration; VLSI design; VLSI processing arrays; diagnosability; dynamic N-modular redundant tuples; fault detection; fault tolerance; low area overhead; majority voting techniques; modular processing arrays; ratioed voter circuit; voting circuit structure; voting level modulation; yield; Circuit faults; Circuit testing; Fault tolerance; Inverters; Logic testing; Redundancy; Sensitivity analysis; Switches; Very large scale integration; Voting;

fLanguage

English

Journal_Title

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Publisher

ieee

ISSN

1057-7122

Type

jour

DOI

10.1109/81.486436

Filename

486436