Pixel-parallel digital CMOS implementation of image segmentation by region growing

The paper proposes a real-time implementation architecture of image segmentation by region growing for grey-scale and colour video or still pictures. The proposed digital CMOS implementation realises pixel-based fully-parallel processing with a cell network. To verify the effectiveness of the proposed architecture, a full-custom test chip in 0.35 /spl mu/m CMOS technology has been designed, containing a cell network for 10/spl times/10 pixels with an integration density of 19.6 pixel/mm/sup 2/. Measured image segmentation times and power dissipation are /spl les/9.5 /spl mu/s and /spl les/36.4 mW at the low clock frequency of 10 MHz. From these results, it is estimated that a cell network for about 50 000/spl sim/100 000 pixels can be integrated on a single chip in a 90 nm CMOS technology, realising very high-speed segmentation of about 300 /spl mu/s at 10 MHz for QVGA-size grey-scale and colour images.