Title :
Digit-serial AB/sup 2/ systolic architecture in GF(2/sup m/)
Author :
Kim, N.-Y. ; Yoo, K.-Y.
Author_Institution :
Dept. of Comput. Eng., Kyungpook Nat. Univ., Taegu, South Korea
Abstract :
The paper presents a digit-serial-in-serial-out systolic architecture for performing an AB/sup 2/ operation in GF(2/sup m/). If the appropriate digit size is selected, the proposed method can meet the throughput requirement of a specific application with minimum hardware. In addition, the area-time complexity of the pipelined digit-serial AB/sup 2/ systolic architecture is approximately 10.9% lower than that of the nonpipelined version when m=160 and L=8.
Keywords :
Galois fields; circuit complexity; pipeline arithmetic; systolic arrays; AB/sup 2/ operation; GF(2/sup m/); area-time complexity; digit-serial-in-serial-out systolic architecture; finite field; pipelined digit-serial systolic architecture;
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings
DOI :
10.1049/ip-cds.20059054
