Non-sequential linear CMOS phase detector for CDR applications

This paper describes a new non-sequential linear phase detector using a standard 0.18 /spl mu/m CMOS process for high-speed clock and data recovery applications. The new phase detector avoids using DFFs or D-latches in order to achieve high operating speeds up to 10 Gbit/s. Its circuit structure is much simpler than the existing half-rate 10 Gbit/s phase detectors reported so far. Consisting of 1 delay cell, 2 XOR gates and 1 AND gate, the proposed PD consumes 34.58 mW. It exhibits a linear characteristic for low jitter operation and avoids half-cycle skew problem inherent in the conventional linear phase detectors. The simple structure of the proposed PD also has the advantage of lower power consumption compared with other PDs reported in the literature.