DocumentCode :
768554
Title :
Universal delay-insensitive systems with buffering lines
Author :
Lee, Jia ; Peper, Ferdinand ; Adachi, Susumu ; Mashiko, Shinro
Author_Institution :
Nanotechnology Group, Nat. Inst. of Inf. & Commun. Technol., Kobe, Japan
Volume :
52
Issue :
4
fYear :
2005
fDate :
4/1/2005 12:00:00 AM
Firstpage :
742
Lastpage :
754
Abstract :
A delay-insensitive (DI) circuit is a type of asynchronous circuit that is robust to arbitrary delays in circuit elements or interconnection lines. This paper presents a new class of DI circuits of which interconnection lines have buffers that may contain multiple signals. We propose a set of three primitive circuit elements each of which has at most four lines for input or output. We prove that this set can be used to construct all valid DI circuits with buffering lines, i.e., that it is universal. Two more sets of three primitives with connectivity four are also presented, and their universality is shown. The limited number of primitives required in each universal set and the low connectivity of the primitives, as compared to previously proposed DI circuits, may facilitate efficient implementation of DI circuits in nanocomputer architectures based on asynchronous cellular automata.
Keywords :
asynchronous circuits; buffer circuits; delays; integrated circuit interconnections; logic devices; asynchronous cellular automata; asynchronous circuit; buffering lines; delay-insensitive circuits; interconnection lines; nanocomputer architecture; primitive circuit elements; universal delay-insensitive systems; Asynchronous circuits; Chip scale packaging; Clocks; Delay systems; Energy consumption; Helium; Integrated circuit interconnections; Robustness; Signal processing; Timing; Asynchronous circuits; delay-insensitive (DI) circuits; module; universality;
fLanguage :
English
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-8328
Type :
jour
DOI :
10.1109/TCSI.2005.844229
Filename :
1417068
Link To Document :
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