Title :
An accurate CMOS sample-and-hold circuit
Author :
Gatti, U. ; Maloberti, F. ; Palmisano, G.
Author_Institution :
Dipartimento di Elettronica, Pavia Univ., Italy
fDate :
1/1/1992 12:00:00 AM
Abstract :
An accurate sample-and-hold (S/H) circuit implemented with a 2-μm double-poly CMOS process is described. Competitive performance in terms of output swing, linearity, and clock feedthrough compensation was obtained using a new circuit topology. The sample and hold operates up to 1 MHz of sampling frequency with less than -60 dB of total harmonic distortion. The accuracy of the held step is better than 0.2 mV. The circuit dissipates 4 mW with a 5-V power supply
Keywords :
CMOS integrated circuits; linear integrated circuits; sample and hold circuits; 1 MHz; 2 micron; 4 mW; 5 V; clock feedthrough compensation; double-poly CMOS process; linearity; output swing; performance; sample-and-hold circuit; sampling frequency; total harmonic distortion; Artificial intelligence; CMOS process; Capacitors; Circuit topology; Clocks; Frequency; Linearity; Operational amplifiers; Power supplies; Sampling methods; Switches; Switching circuits; Total harmonic distortion; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
