Single-event upset in GaAs E/D MESFET logic

Author

Hughlock, B.W. ; LaRue, G.S. ; Johnston, A.H.

Author_Institution

Boeing Aerosp. & Electron., Seattle, WA, USA

Volume

37

Issue

6

fYear

1990

fDate

12/1/1990 12:00:00 AM

Firstpage

1894

Lastpage

1901

Abstract

The single-event upset (SEU) characterization of GaAs enhancement/depletion (E/D) MESFET logic circuits was experimentally performed for five different logic families. The results indicate a large charge collection volume, independent of the logic family. These results can be attributed to a gate edge effect and an enhanced source-drain charge collection mechanism. The consequence of these effects is to increase the upset rate in space by more than two orders of magnitude. Soft-error rates were estimated for each logic family and spanned the range from 2.3×10^-3 to 4.7×10^-4 errors/bit-day

Keywords

III-V semiconductors; field effect integrated circuits; gallium arsenide; integrated circuit testing; integrated logic circuits; ion beam effects; GaAs; LET thresholds; SEU; charge collection volume; enhanced source-drain charge collection mechanism; enhancement/depletion MESFET logic circuits; gate edge effect; ion irradiation; single-event upset; soft error rates; upset rate; Boron; Gallium arsenide; Lithium; Logic circuits; MESFET circuits; Magnesium;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.101206

Filename

101206