Title :
CMOS/SOI hardening at 100 Mrad (SiO2)
Author :
Leray, J.L. ; Dupont-Nivet, E. ; Péré, J.F. ; Coïc, Y.M. ; Raffaelli, M. ; Auberton-Hervé, A.J. ; Bruel, M. ; Giffard, B. ; Margail, J.
Author_Institution :
CEA, Bruyeres-Le-Chatel, France
fDate :
12/1/1990 12:00:00 AM
Abstract :
Hardened CMOS silicon-on-insulator (SOI) 29101 microprocessor elementary cells and transistors were irradiated at levels between 10 Mrad(SiO2) and 1 Grad(SiO2) (60Co and 10-keV X-rays). SIMOX buried oxide behavior in the range of 100 Mrad(SiO 2) and a channel-stopped MOS/SOI structure avoiding lateral leakage current are presented. These two items indicate the feasibility of a CMOS/SOI technology operating in the hundred Mrad(SiO2) range. The SOI structure is described. The total dose radiation effects for 60Co gamma rays and 10-keV X-rays are discussed. Accelerated buried oxide recovery is studied. Irradiation results of a bit-slice microprocessor test chip and elementary cell are presented
Keywords :
CMOS integrated circuits; VLSI; X-ray effects; bit-slice computers; gamma-ray effects; microprocessor chips; radiation hardening (electronics); semiconductor-insulator boundaries; 10 keV; 10-keV X-rays; 1E7 to 1E9 rad; 29101 microprocessor; 60Co gamma rays; CMOS/SOI hardening; CMOS/SOI technology; MOS/SOI structure; SIMOX buried oxide; SOI structure; SiO2-Si; accelerator buried oxide recovery; bit-slice microprocessor test chip; elementary cell; isolation technology; microprocessor elementary cells; total dose radiation effects; Accidents; CMOS technology; Inductors; Insulation; Leakage current; Microprocessors; Reactor instrumentation; Silicon on insulator technology; Testing; X-rays;
Journal_Title :
Nuclear Science, IEEE Transactions on
