Simulation of design dependent failure exposure levels for CMOS ICs

Author

Kaul, N. ; Bhuva, B.L. ; Rangavajjhala, V. ; van der Molen, H. ; Kerns, S.E.

Author_Institution

Dept. of Electr. Eng., Vanderbilt Univ., Nashville, TN, USA

Volume

37

Issue

6

fYear

1990

fDate

12/1/1990 12:00:00 AM

Firstpage

2097

Lastpage

2103

Abstract

The effects of design and bias on the radiation tolerance of ICs are studied, and an automated design tool is described that produces different designs for a logic function and presents important parameters of each design to a circuit designer for tradeoff analysis. It was shown by simulation and experimentally verified that the logic implementation of a circuit and the bias applied during irradiation are significant in determining the radiation tolerance of ICs. The software package aids designers in designing radiation-hard integrated circuits

Keywords

CMOS integrated circuits; circuit layout CAD; integrated circuit technology; integrated logic circuits; logic CAD; radiation hardening (electronics); CMOS ICs; automated design tool; bias effects; design dependent failure exposure levels; design software package; effects of design; logic ICs; logic implementation; radiation tolerance; radiation-hard integrated circuits design; tradeoff analysis; Circuit testing; Degradation; Delay; Design optimization; Failure analysis; Leakage current; Logic circuits; Logic devices; Radiation hardening; Voltage;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.101235

Filename

101235