DocumentCode :
769383
Title :
Design Philosophy and Hardware Implementation for Digital Subscriber Loops
Author :
Ogiwara, Haruo ; Terada, Yasukazu
Author_Institution :
Nippon Telegraph and Telephone Public Corp., Yokosuka, Japan
Volume :
30
Issue :
9
fYear :
1982
fDate :
9/1/1982 12:00:00 AM
Firstpage :
2057
Lastpage :
2065
Abstract :
This paper presents various requirements and configurations in the information network system (INS) NTT´s version of the integrated services digital network (ISDN)- such as field trials, and technologies and equipment design of the digital subscriber loop using balanced wire pairs. The main aspects characterizing digital subscriber loops, are a customer access structure, a digital transmission system on existing subscriber loops, and customer interface. A configuration of two-wire digital subscriber loops with two customer access channels, which is adopted in the field trials, will be described. The time-shared two-wire digital transmission and power feeding methods on subscriber loops are discussed. The common mode rejection ratio (CMRR) is discussed in detail, since CMRR is one of the main factors which affects the transmission ability of balanced wire pairs. A proposed self-clocked four-wire customer interface utilizes time division multiplexing technique. The digital subscriber loop operates on a call-by-call basis for link establishment to avoid excessive power dissipations as well as to avoid impairments caused by crosstalk from other lines within a cable. Its design objectives and implementation are also discussed.
Keywords :
Subscriber networks; DSL; Hardware; ISDN; Information processing; Investments; Optical fiber cables; Power cables; Subscriber loops; Telephony; Wire;
fLanguage :
English
Journal_Title :
Communications, IEEE Transactions on
Publisher :
ieee
ISSN :
0090-6778
Type :
jour
DOI :
10.1109/TCOM.1982.1095709
Filename :
1095709
Link To Document :
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