Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability

In this paper, we present methods for synthesis of sequential circuits for easy testability based on a scheme previously referred to as synthesis for parallel scan. A heuristic is used to achieve maximal merging of the testability logic with the normal combinational logic of the sequential circuit in order to minimize the area overhead. The latches used in the proposed scheme are normal nonscan latches. The synthesis for parallel scan scheme is applied to two different fault models. To facilitate stuck-at-fault testability of sequential circuits, the synthesis for parallel scan method is augmented with a novel structural analysis technique for selection of latches for partial scan with emphasis on minimization of delay overhead. Experimental results on ISCAS ´89 benchmarks resynthesized by our method indicate that one can, in general, achieve the same level of testability with less area and delay overheads, as compared to the conventional structural analysis method for partial scan. A method for synthesizing fully hazard-free robust path-delay fault testable sequential circuits using the concept of synthesis for parallel scan is also presented. When the number of primary inputs of the sequential circuit is at least as large as the number of latches, only normal nonscan latches are required. Experimental results on MCNC and ISCAS ´89 benchmarks show the area overheads to be very reasonable. No previous method could ensure complete robust testability of all path-delay faults in a sequential circuit without assuming a completely enhanced scan, even under the above condition. However, when this condition is not met, i.e., the number of primary inputs is less than the number of latches, we introduce the concept of synthesis for maximally parallel enhanced scan. This still provides complete robust testability, however, at the expense of a higher area overhead