مرکز منطقه ای اطلاع رساني علوم و فناوري - Effect of <formula formulatype="inline"> <img src="/images/tex/653.gif" alt="{\\rm O}_{2}"> </formula> Flow Rate During Channel Layer Deposition on Negative Gate Bias Stress-Induced <formula formulatype="inline"> <img src="/images/tex/509.gif" alt="V

Title :

Effect of ${\\rm O}_{2}$ Flow Rate During Channel Layer Deposition on Negative Gate Bias Stress-Induced $V_{\\r</div> </div> <div class='row'> <div class='leftDiv labelDiv col-xs-4 col-sm-2 fullRecLabelEnglish'>Author : </div><div class='valueDiv leftDirection leftAlign col-xs-8 col-sm-10 fullRecValueEnglish'>Xiang Xiao ; Wei Deng ; Shipeng Chi ; Yang Shao ; Xin He ; Longyan Wang ; Shengdong Zhang</div> </div> <div class='row'> <div class='leftDiv labelDiv col-xs-4 col-sm-2 fullRecLabelEnglish'>Author_Institution : </div><div class='valueDiv leftDirection leftAlign col-xs-8 col-sm-10 fullRecValueEnglish'>Sch. of Electron. & Comput. Eng., Peking Univ., Shenzhen, China</div> </div> <div class='row'> <div class='leftDiv labelDiv col-xs-4 col-sm-2 fullRecLabelEnglish'>Volume : </div><div class='valueDiv leftDirection leftAlign col-xs-8 col-sm-10 fullRecValueEnglish'>60</div> </div> <div class='row'> <div class='leftDiv labelDiv col-xs-4 col-sm-2 fullRecLabelEnglish'>Issue : </div><div class='valueDiv leftDirection leftAlign col-xs-8 col-sm-10 fullRecValueEnglish'>12</div> </div> <div class='row'> <div class='leftDiv labelDiv col-xs-4 col-sm-2 fullRecLabelEnglish'>fYear : </div><div class='valueDiv leftDirection leftAlign col-xs-8 col-sm-10 fullRecValueEnglish'>2013</div> </div> <div class='row'> <div class='leftDiv labelDiv col-xs-4 col-sm-2 fullRecLabelEnglish'>fDate : </div><div class='valueDiv leftDirection leftAlign col-xs-8 col-sm-10 fullRecValueEnglish'>Dec. 2013</div> </div> <div class='row'> <div class='leftDiv labelDiv col-xs-4 col-sm-2 fullRecLabelEnglish'>Firstpage : </div><div class='valueDiv leftDirection leftAlign col-xs-8 col-sm-10 fullRecValueEnglish'>4159</div> </div> <div class='row'> <div class='leftDiv labelDiv col-xs-4 col-sm-2 fullRecLabelEnglish'>Lastpage : </div><div class='valueDiv leftDirection leftAlign col-xs-8 col-sm-10 fullRecValueEnglish'>4164</div> </div> <div class='row'> <div class='leftDiv labelDiv col-xs-4 col-sm-2 fullRecLabelEnglish'>Abstract : </div><div class='valueDiv leftDirection leftAlign col-xs-8 col-sm-10 fullRecValueEnglish'>The effect of O<sub>2</sub> flow rate during the sputtered deposition of channel layer on the negative gate-bias stress (NGBS)-induced threshold voltage (V<sub>th</sub>) instability of a-IGZO TFTs is investigated. It is shown that the negative gate-bias stress results in a negative V<sub>th</sub> shift of the a-IGZO TFTs, and the shift amount decreases with the increase in O<sub>2</sub> flow rate. It is proposed that the V<sub>th</sub> shift originates from the electron-detrapping from the oxygen vacancy-related donor-like states at the channel/dielectric interface. As the O<sub>2</sub> flow rate increases, the density of donor-like states is decreased and the distribution of neutral donor-like states below E<sub>F</sub> is also reduced. Therefore, the amount of Vth shift caused by the positively charged trap states and electrons injecting into the channel from the donor-like states decreases with the O<sub>2</sub> flow rate increase. It is also shown experimentally that while the electrical characteristics of the a-IGZO TFTs are generally improved with the O<sub>2</sub> flow rate increase, they are degraded if an excess O<sub>2</sub> is introduced. An optimal O<sub>2</sub>/Ar flow rate ratio of about 5 sccm/45 sccm is suggested to make a trade-off between the electrical performances and the gate-bias stress-induced V<sub>th</sub> instability.</div> </div> <div class='row'> <div class='leftDiv labelDiv col-xs-4 col-sm-2 fullRecLabelEnglish'>Keywords : </div><div class='valueDiv leftDirection leftAlign col-xs-8 col-sm-10 fullRecValueEnglish'>negative bias temperature instability; thin film transistors; NGBS-induced threshold voltage; a-IGZO TFT; channel layer deposition; channel/dielectric interface; charged trap states; electron detrapping; flow rate; gate bias stress induced instability; negative gate bias stress; neutral donor like states; vacancy related donor-like states; Educational institutions; Logic gates; Sputtering; Stress; Thin film transistors; Threshold voltage; <formula formulatype=$ ${rm O}_{2}$ flow rate; Amorphous indium-gallium-zinc-oxide (a-IGZO); donor-like states; instability; thin film transistors (TFTs);