Effect of Damage in Source and Drain on the Endurance of a 65-nm-Node NOR Flash Memory

On 12-in wafers of 65-nm-node floating gate NOR flash memory, charge pumping measurements show that compared to those on the edge dies (type A), the devices on the central dies (type B) have more severe damage in the source (S) and drain (D) regions. In type-B devices, the worse damage is due to the generation of interface traps in the S/channel overlapping region and the generation of bulk traps in the S and D junction region. In type-A devices, the damage is much weaker. The generation of interface traps is observed in the S/channel overlapping region. However, it is hardly measurable on the D side. The endurance characteristics have been measured in these two kinds of devices under the channel hot electron program and Fowler-Nordheim erase. In type-B devices, after program/erase cycling the memory window closure is more serious and the junction leakage also degrades greatly with the generation of a lot of bulk traps at S and D regions. The damage in fresh devices is suggested to be due to the plasma etching processes.