Title :
Design of multioutput CMOS combinational logic circuits for robust testability
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fDate :
11/1/1989 12:00:00 AM
Abstract :
The author proposes a testable design for multioutput functions using parity gates that always produces a realization with robust tests. The use of parity gates allows more logic sharing among various outputs than would have been possible otherwise. The solution presented here has the ability to accommodate any fan-in restriction and grow in number of levels. The new design is well suited for multioutput circuits
Keywords :
CMOS integrated circuits; integrated circuit testing; integrated logic circuits; logic design; logic testing; CMOS; combinational logic circuits; multioutput circuits; multioutput functions; parity gates; robust testability; testable design; CMOS logic circuits; CMOS technology; Circuit faults; Circuit testing; Combinational circuits; Delay; Electrical fault detection; Fault detection; Logic testing; Robustness;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
