Title :
A Calibrated Phase/Frequency Detector for Reference Spur Reduction in Charge-Pump PLLs
Author :
Charles, Cameron T. ; Allstot, David J.
Author_Institution :
Dept. of Electr. Eng., Univ. of Washington, Seattle, WA
Abstract :
This brief presents a new technique for minimizing reference spurs in a charge-pump phase-locked loop (PLL) while maintaining dead-zone-free operation. The proposed circuitry uses a phase/frequency detector with a variable delay element in its reset path, with the delay length controlled by feedback from the charge-pump. Simulations have been performed with several PLLs to compare the proposed circuitry with previously reported techniques. The proposed approach shows improvements over previously reported techniques of 12 and 16 dB in the two closest reference spurs
Keywords :
phase detectors; phase locked loops; voltage-controlled oscillators; charge-pump phase locked loop; delay length; frequency detector; phase detector; reference spur reduction; reset path; variable delay element; Charge pumps; Circuit simulation; Delay; Digital systems; Flip-flops; Phase detection; Phase frequency detector; Phase locked loops; Voltage control; Voltage-controlled oscillators; Phase/frequency detector (PFD); phase-locked loop (PLL); voltage control oscillator (VCO);
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2006.880030
