A Calibrated Phase/Frequency Detector for Reference Spur Reduction in Charge-Pump PLLs

This brief presents a new technique for minimizing reference spurs in a charge-pump phase-locked loop (PLL) while maintaining dead-zone-free operation. The proposed circuitry uses a phase/frequency detector with a variable delay element in its reset path, with the delay length controlled by feedback from the charge-pump. Simulations have been performed with several PLLs to compare the proposed circuitry with previously reported techniques. The proposed approach shows improvements over previously reported techniques of 12 and 16 dB in the two closest reference spurs