• DocumentCode
    772051
  • Title

    Architecture Design of Context-Based Adaptive Variable-Length Coding for H.264/AVC

  • Author

    Chen, Tung-Chien ; Huang, Yu-Wen ; Tsai, Chuan-Yung ; Hsieh, Bing-Yu ; Chen, Liang-Gee

  • Author_Institution
    Dept. of Electr. Eng., DSP/IC Design Lab., Taipei
  • Volume
    53
  • Issue
    9
  • fYear
    2006
  • Firstpage
    832
  • Lastpage
    836
  • Abstract
    Context-based adaptive variable-length coding (CAVLC) is a new and important feature of the latest video coding standard, H.264/AVC. The direct VLSI implementation of CAVLC modified from the conventional run-length coding architecture will lead to low throughput and utilization. In this brief, an efficient CAVLC design is proposed. The main concept is the two-stage block pipelining scheme for parallel processing of two 4 times 4 blocks. When one block is processed by the scanning engine to collect the required symbols, its previous block is handled by the coding engine to translate symbols into bitstream. Our dual-block-pipelined architecture doubles the throughput and utilization of CAVLC at high bit rates. Moreover, a zero skipping technique is adopted to reduce up to 90% of cycles at low bit rates. Last but not least, Exp-Golomb coding for other general symbols and bitstream encapsulation for the network abstraction layer are integrated with CAVLC as a complete H.264/AVC baseline profile entropy coder. Simulation shows that our design is capable of real-time processing for 1920 times 1088 30-fps videos with 23.6 K logic gates at 100 MHz
  • Keywords
    VLSI; integrated circuit design; logic design; logic gates; pipeline processing; variable length codes; video coding; 100 MHz; Exp-Golomb coding; H.264 coding; VLSI; adaptive coding; bitstream encapsulation; block pipelining scheme; coding engine; context-based coding; dual-block-pipelined architecture; entropy coder; parallel processing; real-time processing; scanning engine; variable-length coding; video coding; zero skipping; Automatic voltage control; Bit rate; Encapsulation; Engines; Entropy; Parallel processing; Pipeline processing; Throughput; Very large scale integration; Video coding; Context-based adaptive variable-length coding (CAVLC); H.264/AVC; VLSI architecture;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems II: Express Briefs, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-7747
  • Type

    jour

  • DOI
    10.1109/TCSII.2006.880014
  • Filename
    1705049