Title :
Conflict-free access for streams in multimodule memories
Author :
Valero, Mateo ; Lang, Tomás ; Peiron, Montse ; Ayguadé, Eduard
Author_Institution :
Dept. d´´Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
fDate :
5/1/1995 12:00:00 AM
Abstract :
Address transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free access for streams with constant stride. However, this is achieved only for some strides. In this paper, we extend these schemes to achieve this conflict-free access for a larger number of strides. The basic idea is to perform an out-of-order access to a stream of fixed length. This stream is then stored in a local memory and used in subsequent instructions. This mode of operation is suitable for vector processors and for processors with decoupled access. The scheme and mode of operation proposed produce the largest possible number of conflict-free strides. Memory systems with any ratio between the number of memory modules and memory latency are considered. The hardware for address calculations and access control is described and shown to be of similar complexity as that required for access in order
Keywords :
computational complexity; memory architecture; vector processor systems; address transformation schemes; complexity; conflict-free access; linear transformations; local memory; memory latency; memory modules; multimodule memories; out-of-order access; skewing; streams; Access control; Bandwidth; Computer Society; Delay; Frequency; Hardware; Interleaved codes; Out of order; Throughput; Vector processors;
Journal_Title :
Computers, IEEE Transactions on