• DocumentCode
    772537
  • Title

    Learning hardware using multiple-valued logic - Part 2: Cube calculus and architecture

  • Author

    Perkowski, Marek ; Foote, David ; Chen, Qihong ; Al-Rabadi, Anas ; Jozwiak, Lech

  • Author_Institution
    Portland State Univ., OR, USA
  • Volume
    22
  • Issue
    3
  • fYear
    2002
  • Firstpage
    52
  • Lastpage
    61
  • Abstract
    For Part 1 see ibid. vol.22, no.3 (2002). A massively parallel reconfigurable processor speeds up the logic operators performed in the learning hardware. The approach uses combinatorial synthesis methods developed within the framework of the logic synthesis approach in digital-circuit-design automation
  • Keywords
    learning systems; multivalued logic; parallel architectures; reconfigurable architectures; symbol manipulation; combinatorial synthesis; cube calculus; learning hardware; logic synthesis; massively parallel architecture; multiple-valued logic; reconfigurable hardware; symbolic learning; Arithmetic; Calculus; Encoding; Hamming distance; Hardware; Logic; Set theory;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/MM.2002.1013304
  • Filename
    1013304
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=772537