• DocumentCode
    772607
  • Title

    50-Gb/s 4-b multiplexer/demultiplexer chip set using InP HEMTs

  • Author

    Sano, Kimikazu ; Murata, Koichi ; Sugitani, Suehiro ; Sugahara, Hirohiko ; Enoki, Takatomo

  • Author_Institution
    NTT Photonics Labs., NTT Corp., Kanagawa, Japan
  • Volume
    38
  • Issue
    9
  • fYear
    2003
  • Firstpage
    1504
  • Lastpage
    1511
  • Abstract
    A 50-Gb/s 4:1 multiplexer (MUX) and 1:4 demultiplexer (DEMUX) chip set using InP high electron mobility transistors (HEMTs) is described. In order to achieve wide-range bit-rate operation from several to 50 Gb/s, timing design inside the ICs was precisely executed. The packaged MUX operated from 4 to 50Gb/s with >1-Vpp output amplitude, and the DEMUX exhibited >180° phase margin from 4 to 50 Gb/s for 231-1 pseudorandom bit sequence (PRBS). Furthermore, 50-Gb/s back-to-back error-free operation for 231-1 PRBS was confirmed with the packaged MUX and DEMUX.
  • Keywords
    HEMT integrated circuits; III-V semiconductors; demultiplexing equipment; indium compounds; multiplexing equipment; 4 bit; 4 to 50 Gbit/s; InP; InP HEMT IC; multiplexer/demultiplexer chip set; pseudorandom bit sequence; timing design; Circuits; Delay; Flip-flops; HEMTs; Heterojunction bipolar transistors; Indium phosphide; MODFETs; Multiplexing; Packaging; Timing;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.2003.815923
  • Filename
    1225791
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=772607