Reduction of PN junction leakage current by using poly-Si interlayered SOI wafers

Author

Horiuchi, Masatada ; Ohoyu, Kiyonori

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

Volume

42

Issue

5

fYear

1995

fDate

5/1/1995 12:00:00 AM

Firstpage

876

Lastpage

882

Abstract

A new type of silicon-on-insulator (SOI) structure was fabricated by using direct bonding technology to bury multilayered films consisting of poly-Si, Si₃N₄, and SiO₂. The cross-sectional structures were analyzed by using SIMS, micro-Raman spectroscopy, and spreading resistance methods. Both the area components and the perimeter components of the PN-junction leakage current were reduced more than 10 fold in structures that had a poly-Si interlayer just beneath the active-devices to act as a gettering site. The leakage current was a function of tensile strength in the SOI layer and was easily controlled with a suitable combination of interlayered insulators

Keywords

elemental semiconductors; getters; insulating thin films; leakage currents; p-n junctions; silicon; silicon-on-insulator; tensile strength; wafer bonding; SIMS; Si-Si₃N₄-SiO₂; buried multilayered films; direct bonding technology; gettering site; interlayered insulators; leakage current reduction; micro-Raman spectroscopy; p-n junction leakage current; poly-Si interlayered SOI wafers; polysilicon interlayer; spreading resistance method; tensile strength; Crystalline materials; Fabrication; Gettering; Impurities; Leakage current; Random access memory; Semiconductor films; Silicon on insulator technology; Stress control; Wafer bonding;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.381983

Filename

381983