Performance Improvement of a Binary Quantized All-Digital Phased-Locked Loop with a New Aided-Acquisition Technique

A nonuniform sampling digital phase-locked loop (DPLL) is proposed with a sequential loop filter, in which two additional phase comparators are added conjointly with an estimation-decision circuit controlling the two distinct modes, acquisition and tracking, in which the loop is to work. These additions provide more freedom to deal with the conflicting requirements of minimum acquisition time and maximum noise rejection in the presence or absence of frequency drift. Using a pseudo-two-dimensional random-walk filter, the stationary phase-error variance and the mean acquisition time have been evaluated by means of a numerical analysis. The comparison between the theoretical analysis and the experiments has proven to be very satisfactory. Substantial reduction of the acquisition time, without severely degrading the noise reduction performance, has been achieved. The improved ability of this modified loop to track frequency drift was also demonstrated. A digital loop "quasi-bandwidth" measure was used in the evaluation of the loop performance, thus allowing for a comparison with other digital loops and to a limited extent with a first-order analog loop. The usual difference in performance favoring the analog loop for high signal-to-noise ratio is shown to be substantially reduced and can be lowered by an appropriate choice of parameters.