A new grounded lamination gate (GLG) for diminished fringe-capacitance effects in high-/spl kappa/ gate-dielectric MOSFETs

Author

Kumar, M. Jagadesh ; Venkataraman, Vivek ; Gupta, Sumeet Kumar

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol., New Delhi

Volume

53

Issue

10

fYear

2006

Firstpage

2578

Lastpage

2581

Abstract

A grounded lamination gate (GLG) structure for high-kappa gate-dielectric MOSFETs is proposed, with grounded metal plates in the spacer oxide region. Two-dimensional device simulations performed on the new structure demonstrate a significant improvement with respect to the threshold voltage roll-off with increasing gate-dielectric constant (due to parasitic internal fringe capacitance), keeping the equivalent oxide thickness same. A simple fabrication procedure for the GLG MOSFET is also presented

Keywords

MOSFET; high-k dielectric thin films; permittivity; 2D device simulations; diminished fringe-capacitance effects; equivalent oxide thickness; gate-dielectric constant; grounded lamination gate; grounded metal plates; high-K gate-dielectric MOSFET; parasitic internal fringe capacitance; silicon-on-insulator; spacer oxide region; threshold voltage; Conducting materials; Dielectric devices; Fabrication; Lamination; MOSFETs; Medical simulation; Parasitic capacitance; Permittivity; Silicon on insulator technology; Threshold voltage; High-; MOSFET; internal fringe capacitance; silicon-on-insulator (SOI); simulation; threshold voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2006.882268

Filename

1705112