DocumentCode
772767
Title
Novel pipelined serial/parallel multiplier
Author
Ait-Boudaoud, D. ; Ibrahim, M.K. ; Hayes-Gill, B.R.
Author_Institution
Dept. of Electr. & Electron. Nottingham Univ., UK
Volume
26
Issue
9
fYear
1990
fDate
4/26/1990 12:00:00 AM
Firstpage
582
Lastpage
583
Abstract
A novel unidirectional pipelined serial/parallel multiplier (PSPM) is presented. This design has halved the initial delay and reduces the number of latches by 10% of the conventional structure. An area-time criteria is used to compare the new architecture with the old PSPM.
Keywords
multiplying circuits; pipeline processing; PSPM; area-time criteria; initial delay; latches; pipelined serial/parallel multiplier;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19900381
Filename
48767
Link To Document