A programmable state machine architecture for packet processing

The Internet is expanding rapidly and constantly adding new protocols and features. To shorten the design cycle, many companies have adopted a common hardware platform for a variety of products. In these products, specialized packet processors tailored for packet processing handle multiple protocols and feature changes. A packet processor usually incorporates multiple RISC engines that are configurable as several instances of parallel processors, working simultaneously or in a pipelined fashion. In either approach, packet processors are complex and expensive. Packet processing has many levels of programmability requirements. Some tasks require only mild programmability and can´t justify the use of a full-fledged packet processor. A finite scare machine (FSM), on the other hand, has high performance but cannot adapt to protocol changes. The solution is something in between: fast, programmable, but not as complicated as a packet processor. A programmable state machine (PSM) is such an idea.