A new built-in TPG method for circuits with random pattern resistant faults

Author

Kavousianos, Xrysovalantis ; Bakalis, Dimitris ; Nikolos, Dimitris ; Tragoudas, Spyros

Author_Institution

Dept. of Comput. Eng. & Inf., Patras Univ., Greece

Volume

21

Issue

7

fYear

2002

fDate

7/1/2002 12:00:00 AM

Firstpage

859

Lastpage

866

Abstract

The partition of the inputs of a circuit under test (CUT) into groups of compatible inputs reduces the size of a test pattern generator and the length of the test sequence for built-in self-test (BIST) applications. In this paper, a new test-per-clock BIST scheme is proposed which is based on multiple input partitions. The test session consists of two or more phases, and a new grouping is applied during each test phase. Using the proposed method a CUT can be tested at-speed and complete fault coverage (100%) is achieved with a small number of test vectors and small area overhead. Our experiments show that the proposed technique compares favorably to the already known techniques

Keywords

automatic test pattern generation; built-in self test; combinational circuits; integrated circuit testing; logic testing; assigning logic module; built-in TPG method; circuit under test; combinational circuits; complete fault coverage; flip-flops; inputs partition; multiple input partitions; phase selection module; random pattern resistant faults; small area overhead; test pattern generator size; test sequence length; test-per-clock BIST scheme; two-port register; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Design automation; Digital systems; Polynomials; Strontium; System testing; Test pattern generators;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.2002.1013898

Filename

1013898