NMOSFET ESD self-protection strategy and underlying failure mechanism in advanced 0.13-μm CMOS technology

Author

Salman, Akram ; Gauthier, Robert ; Stadler, Wolfgang ; Esmark, Kai ; Muhammad, Mujahid ; Putnam, Chris ; Ioannou, Dimitris E.

Author_Institution

Dept. of Electr. & Comput. Eng., George Mason Univ., Fairfax, VA, USA

Volume

2

Issue

1

fYear

2002

fDate

3/1/2002 12:00:00 AM

Firstpage

2

Lastpage

8

Abstract

In this paper, the high current characteristics encountered during electrostatic discharge (ESD) stress using nMOS/L_npn protection devices in a 0.13-μm CMOS technology are investigated for different device parameters: channel length, channel width, gate-oxide thickness, and drain/source contact to gate (DCG/SCG) spacing. From leakage current measurements following ESD stress, it is concluded that the shorter (0.13 μm) devices fail because of source/drain filamentation, whereas longer (0.3 μm) devices with thin (22 Å) oxide gate fail because of oxide breakdown. This conclusion is consistent with and supported by numerical simulations of the electric field. It is also supported by the observed effect of hot carrier stress on I_t2. Hot carrier stress experiments additionally revealed that ESD stress can and does affect subsequent hot carrier degradation of the device

Keywords

CMOS integrated circuits; MOSFET; dielectric thin films; electrostatic discharge; failure analysis; hot carriers; integrated circuit reliability; integrated circuit testing; numerical analysis; protection; semiconductor device breakdown; 0.13 micron; 0.3 micron; 22 angstrom; CMOS technology; ESD failure mechanisms; ESD protection; ESD stress; GG-MOSFET; SiO₂-Si; channel length; channel width; device parameters; drain contact to gate spacing; electric field; electrostatic discharge stress; gate-oxide thickness; grounded gate nMOSFET; high current characteristics; hot carrier degradation; hot carrier stress; leakage current measurements; nMOS/L_npn protection devices; nMOSFET ESD self-protection strategy; numerical simulations; oxide breakdown; source contact to gate spacing; source/drain filamentation; thin gate oxide; underlying failure mechanism; CMOS technology; Current measurement; Electrostatic discharge; Electrostatic measurements; Hot carriers; Leakage current; MOS devices; MOSFET circuits; Protection; Stress;

fLanguage

English

Journal_Title

Device and Materials Reliability, IEEE Transactions on

Publisher

ieee

ISSN

1530-4388

Type

jour

DOI

10.1109/TDMR.2002.1014666

Filename

1014666