DocumentCode :
773983
Title :
An Optimum Algorithm for Compacting Error Traces for Efficient Design Error Debugging
Author :
Yen, Chia-Chih ; Jou, Jing-Yang
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu
Volume :
55
Issue :
11
fYear :
2006
Firstpage :
1356
Lastpage :
1366
Abstract :
Diagnosing counterexamples with error traces has acted as one of the most critical steps in functional verification. Unfortunately, error traces are normally very lengthy such that designers need to spend considerable effort to understand them. To alleviate the designers´ burden for debugging, we present a SAT-based algorithm for reducing the lengths of error traces. The algorithm performs the paradigm of the binary search algorithm to halve the search space recursively. Furthermore, it applies a novel theorem to guarantee gaining the shortest lengths for the error traces. Based on the optimum algorithm, we develop two robust heuristics to handle real designs. Experimental results demonstrate that our approaches greatly surpass previous work and, indeed, have promising solutions
Keywords :
computability; formal verification; logic design; logic testing; SAT-based algorithm; binary search algorithm; design error debugging; functional verification; optimum algorithm; satisfiability; Algorithm design and analysis; Compaction; Debugging; Hardware; Observability; Phase detection; Robustness; Signal design; Testing; Writing; Verification; diagnosis; error checking; satisfiability.; simulation;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.2006.174
Filename :
1705445
Link To Document :
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