An Energy-Efficient Reconfigurable Baseband Processor for Wireless Communications

Author

Poon, Ada S Y

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Illinois, Urbana-Champaign, IL

Volume

15

Issue

3

fYear

2007

fDate

3/1/2007 12:00:00 AM

Firstpage

319

Lastpage

327

Abstract

Most existing techniques for reconfigurable processors focus on the computation model. This paper focuses on increasing the granularity of configurable units without compromising flexibility. This is carried out by matching the granularity to the degree-of-freedom processing in most wireless systems. A design flow that accelerates the exploration of tradeoffs among various architectures for the configurable unit is discussed. A prototype processor is implemented using the Intel 0.13-mum CMOS standard cell library. The estimated energy efficiency is in the same order as dedicated hardware implementations

Keywords

CMOS integrated circuits; integrated circuit design; microprocessor chips; reconfigurable architectures; wireless LAN; 0.13 micron; CMOS standard cell library; reconfigurable baseband processors; wireless communications; Acceleration; Baseband; CMOS process; Computational modeling; Computer architecture; Energy efficiency; Hardware; Libraries; Prototypes; Wireless communication; Degrees of freedom (DOF); low-power design; reconfigurable processors; wireless communication systems;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2007.893619

Filename

4154775