DocumentCode :
774197
Title :
Multiplierless Implementations of MF/DTMF Receivers
Author :
Agarwal, R.C. ; Sudhakar, R. ; Agrawal, B.P.
Author_Institution :
IBM T.J. Watson Res. Ctr., Yorktown Heights, NY, USA
Volume :
32
Issue :
7
fYear :
1984
fDate :
7/1/1984 12:00:00 AM
Firstpage :
839
Lastpage :
847
Abstract :
The ever-increasing use of VLSI in telecommunications systems is leavening the search of new algorithms for task realizations suited to VLSI implementations of systems. Toward this search, the paper presents implementations for MF/DTMF receivers, which are based on multiplierless basic filters or primitive VLSI cells such as 
, 
, and 
. These implementations require parallel processing and are designed to meet the requirements of a switching system.
, , and . These implementations require parallel processing and are designed to meet the requirements of a switching system.Keywords :
Receivers; Algorithm design and analysis; Digital filters; Digital signal processing chips; Frequency; Parallel processing; Process design; Signal design; Signal processing algorithms; Switching systems; Very large scale integration;
fLanguage :
English
Journal_Title :
Communications, IEEE Transactions on
Publisher :
ieee
ISSN :
0090-6778
Type :
jour
DOI :
10.1109/TCOM.1984.1096147
Filename :
1096147
Link To Document :
