Technique to minimise area overhead for delay-driven clustering

The paper presents heuristics to the area overhead for delay-driven clustering of combinational circuits under I/O and area constraints. The authors start with a clustering which aims at minimal path delay. They then propose several set covering heuristics to minimise the number of clusters while satisfying the constraints and preserving the timing. Moreover, they propose a hierarchical clustering method to explore global area-delay tradeoff. The methods have been tested on benchmark circuits and displayed excellent results