Title :
Analysis and modelling of parasitic substrate coupling in CMOS circuits
Author :
Aragonés, X. ; Moll, F. ; Roca, M. ; Rubio, A.
Author_Institution :
Dept. of Electron. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain
fDate :
10/1/1995 12:00:00 AM
Abstract :
Analysis of the substrate coupling in integrated circuits is done taking into account technology and layout parameters for different types and location of transistors using a device-level simulator. The noise coupling tendencies of IC scaling are analysed, following interest in advanced technologies. The potential for permanent errors is shown in the case of a RAM cell. A circuit-level model for the coupling mechanism is proposed. The implementation of an IC for experimentation, and the measurements obtained, are discussed
Keywords :
CMOS integrated circuits; capacitance; integrated circuit modelling; integrated circuit noise; substrates; CMOS circuits; IC modelling; IC scaling; RAM cell; circuit-level model; device-level simulator; integrated circuits; noise coupling; parasitic substrate coupling; permanent errors;
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings -
DOI :
10.1049/ip-cds:19952164
