Optimisation of high-performance gates in AlGaAs/GaAs quantum-well technology

Ultra-high-speed logic gates are proposed using heterostructure field-effect transistors. A simple noise margin optimisation method is applied to improve the performance in terms of noise margin and delay. A 16-bit binary carry look-ahead adder is then used as a demonstrator circuit to show the advantages of the logic gates over the standard direct coupled FET logic implementation