Routing for reliable manufacturing

Author

Huijbregts, Ed P. ; Xue, Hua ; Jess, Jochen A G

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

Volume

8

Issue

2

fYear

1995

fDate

5/1/1995 12:00:00 AM

Firstpage

188

Lastpage

194

Abstract

The impact of spot defects on the susceptibility for electrical failure of a net is analyzed. Based on this analysis, a general routing cost function is presented, in which the manufacturability of a net is taken into account in conjunction with traditional routing objectives. The new cost function, relating the process spot defects to the routing procedure has been implemented. Failure probabilities are analyzed for the benchmark layouts obtained by our routing tool using both the original cost function and the new cost function. The results show that the failure probability of a layout is significantly decreased if the spot defect mechanism is taken into account in the routing procedure, while the area of the layout is kept constant

Keywords

economics; failure analysis; integrated circuit layout; integrated circuit manufacture; integrated circuit reliability; network routing; benchmark layouts; cost function; electrical failure; failure probabilities; net; process spot defects; reliable manufacturing; routing; Cost function; Fabrication; Failure analysis; Joining processes; Laboratories; Manufacturing; Routing; Tree graphs; Very large scale integration;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/66.382282

Filename

382282