DocumentCode :
775050
Title :
Design of 10-nm-scale recessed asymmetric Schottky barrier MOSFETs
Author :
Yaohui Zhang ; Jun Wan ; Wang, K.L. ; Bich-Yen Nguyen
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Volume :
23
Issue :
7
fYear :
2002
fDate :
7/1/2002 12:00:00 AM
Firstpage :
419
Lastpage :
421
Abstract :
We have proposed and simulated a new 10-nm and sub-10 nm n-MOSFET that has a recessed channel and asymmetric source/drain Schottky Contacts (RASC MOSFETs). The recessed channel can effectively suppress short-channel effects, and the asymmetric source/drain contacts in which a higher Schottky barrier at the source contact can yield smaller off-state current while a lower Schottky barrier at the drain can yield larger on-state current. The simulated results show that the device can exhibit an on/off ratio as high as 106 and an on-state current of 393 μA/μm with a supply voltage of 1.0 V. Furthermore, the parameters of RASC MOSFETs are rather insensitive to size variations. These characteristics make the 10-nm or even sub-10 nm transistors potentially suitable for logic and memory applications.
Keywords :
MOSFET; Schottky barriers; leakage currents; semiconductor device models; tunnelling; 10 nm; DESSIS 7.0; Schottky barrier MOSFET; asymmetric source/drain contacts; gate-induced-drain leakage; nonlocal tunneling models; off-state current; on-state current; recessed channel; short-channel effects; silicides; simulation; transfer characteristics; Dielectric substrates; Doping; Leakage current; Logic; MOSFET circuits; Schottky barriers; Silicides; Silicon; Tunneling; Voltage;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/LED.2002.1015225
Filename :
1015225
Link To Document :
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