Title :
A taxonomy of reconfiguration techniques for fault-tolerant processor arrays
Author :
Chean, Mengly ; Fortes, Jose A B
Author_Institution :
Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
Focuses on the characterization and classification of reconfiguration techniques. The techniques are differentiated according to the type of redundancy (time or hardware), allocation of redundancy (local or global), replacement unit, (processor or a set of processors), switching domain (global or local), and switching implementation (switching element, bus, or network). Typical techniques from four major classes-set switching, processor switching, local redundancy, and time redundancy-are reviewed. The proposed taxonomy can be used as a guide for future research in design and analysis of reconfiguration schemes.<>
Keywords :
cellular arrays; fault tolerant computing; multiprocessor interconnection networks; redundancy; bus; domain; fault-tolerant processor arrays; global redundancy; global switching; hardware redundancy; local redundancy; local switching domain; network; processor; processor switching; reconfiguration techniques; redundancy allocation; redundancy type; replacement unit; set switching; switching element; switching implementation; time redundancy; Classification tree analysis; Degradation; Fault tolerance; Hardware; Large scale integration; Manufacturing processes; Redundancy; Taxonomy; Very large scale integration;
