Interprocessor communication in synchronous multiprocessor digital signal processing chips

The authors discuss interprocessor communication in synchronous multiprocessor DSP (digital signal processing) chips, the types of systems that are synthesized by the Cathedral II silicon compiler. A model for the data flow between two processors is presented. A number of architectural possibilities are discussed. Key concepts are a double-buffered memory cell and an extended method of pointer addressing. This method leads to the definition of `once in, once out´ communication, as opposed to conventional FIFO (first in, first out) buffering. The minimization of the buffer size by skewing the operation of the processors is worked out for specific important types of communication. The proposed techniques have been implemented in a synthesis tool which is part of Cathedral II. The practical significance of the work is illustrated with several examples