DocumentCode
7751
Title
SIMD Acceleration for HEVC Decoding
Author
Chi Ching Chi ; Alvarez-Mesa, Mauricio ; Bross, Benjamin ; Juurlink, Ben ; Schierl, Thomas
Author_Institution
Embedded Syst. Archit. Group, Tech. Univ. of Berlin, Berlin, Germany
Volume
25
Issue
5
fYear
2015
fDate
May-15
Firstpage
841
Lastpage
855
Abstract
Single instruction multiple data (SIMD) instructions have been commonly used to accelerate video codecs. The recently introduced High Efficiency Video Coding (HEVC) codec like its predecessors is based on the hybrid video codec principle and, therefore, is also well suited to be accelerated with SIMD. In this paper we present the SIMD optimization for the entire HEVC decoder for all major SIMD instruction set architectures. Evaluation has been performed on 14 mobile and PC platforms covering most major architectures released in recent years. With SIMD, up to 5× speedup can be achieved over the entire HEVC decoder, resulting in up to 133 and 37.8 frames/s on average on a single core for Main profile 1080p and Main10 profile 2160p sequences, respectively.
Keywords
optimisation; parallel processing; video coding; HEVC decoding; SIMD acceleration; SIMD instruction set architectures; SIMD instructions; SIMD optimization; high efficiency video coding; single instruction multiple data; video codecs; Acceleration; Decoding; Interpolation; Optimization; Program processors; Standards; Video coding; AVX; Advanced Vector Extensions (AVX); H.265; HEVC; High Efficiency Video Coding (HEVC); NEON; SIMD; SSE; Streaming SIMD Extensions (SSE); UHD; single instruction multiple data (SIMD); ultrahigh definition (UHD);
fLanguage
English
Journal_Title
Circuits and Systems for Video Technology, IEEE Transactions on
Publisher
ieee
ISSN
1051-8215
Type
jour
DOI
10.1109/TCSVT.2014.2364413
Filename
6933880
Link To Document