• DocumentCode
    775337
  • Title

    Comments on the metastable behavior of mismatched CMOS latches

  • Author

    Jeppson, K.O.

  • Author_Institution
    Dept. of Solid State Electron., Chalmers Univ. of Technol., Goteborg
  • Volume
    31
  • Issue
    2
  • fYear
    1996
  • fDate
    2/1/1996 12:00:00 AM
  • Firstpage
    275
  • Lastpage
    277
  • Abstract
    Further insight into the use of state diagrams as tools for understanding the metastable behavior of CMOS latches is provided, The effect of mismatched device parameters and unbalanced load capacitances on the metastable behavior of CMOS latches are studied using both small and large signal analyses. The results agree well with circuit simulations
  • Keywords
    CMOS logic circuits; capacitance; circuit stability; diagrams; flip-flops; network analysis; time-domain analysis; large signal analysis; metastable behavior; mismatched CMOS latches; small signal analysis; state diagrams; unbalanced load capacitances; Capacitance; Circuit simulation; Equations; Flip-flops; Inverters; Latches; Metastasis; Signal analysis; Single event upset; Voltage;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.488008
  • Filename
    488008
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=775337