Title :
Comments on the metastable behavior of mismatched CMOS latches
Author_Institution :
Dept. of Solid State Electron., Chalmers Univ. of Technol., Goteborg
fDate :
2/1/1996 12:00:00 AM
Abstract :
Further insight into the use of state diagrams as tools for understanding the metastable behavior of CMOS latches is provided, The effect of mismatched device parameters and unbalanced load capacitances on the metastable behavior of CMOS latches are studied using both small and large signal analyses. The results agree well with circuit simulations
Keywords :
CMOS logic circuits; capacitance; circuit stability; diagrams; flip-flops; network analysis; time-domain analysis; large signal analysis; metastable behavior; mismatched CMOS latches; small signal analysis; state diagrams; unbalanced load capacitances; Capacitance; Circuit simulation; Equations; Flip-flops; Inverters; Latches; Metastasis; Signal analysis; Single event upset; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
